1. Field of the Invention
The present invention relates to an ADPLL frequency synthesizer included in a radio communication device, a radio measurement device or the like.
2. Description of the Background Art
In an ADPLL (All Digital Phase-Locked Loop) frequency synthesizer covering a wide band, when an oscillatory frequency of a digital controlled oscillator (DCO) changes, a control sensitivity KDCO of the digital controlled oscillator is changed accordingly. Thus, a phase noise characteristic with respect to the oscillatory frequency of the digital controlled oscillator is also changed.
Conventionally, the ADPLL frequency synthesizer included in a radio communication device is disclosed in FIG. 31 of the specification (patent document 1) of US Patent Application Publication No. 2003/0133522, for example. FIG. 6 is a block diagram illustrating a structure of a conventional ADPLL frequency synthesizer 100 disclosed in patent document 1.
In a digital controlled oscillator (DCO) 101 shown in FIG. 6, when an oscillatory frequency thereof changes, a control sensitivity KDCO of the digital controlled oscillator accordingly changes. Therefore, a control sensitivity estimation section 102 for estimating the control sensitivity KDCO of the digital controlled oscillator 101 operates at all times. Furthermore, in the conventional ADPLL frequency synthesizer 100, a DCO Gain normalization circuit 111 for correcting the control sensitivity KDCO of the digital controlled oscillator 101 is provided prior to the digital controlled oscillator 101, thereby preventing a phase noise characteristic from being changed even if the control sensitivity KDCO changes.
The above-described state is represented by a formula. A phase domain transfer function Hcl of the conventional ADPLL frequency synthesizer 100 is represented by the following formula [1]. Note that α and ρ each represents a filter coefficient of a loop filter 103, and fR represents a frequency of a reference signal FREF.
                                          H            cl                    ⁡                      (            s            )                          =                  N          ⁢                                                    α                ⁢                                                                  ⁢                                  f                  R                                            ⁣                                                ·                  s                                +                                  ρ                  ⁢                                                                          ⁢                                      f                    R                    2                                                                                                      s                2                            +                              α                ⁢                                                                  ⁢                                                      f                    R                                    ·                  s                                            +                              ρ                ⁢                                                                  ⁢                                  f                  R                  2                                                                                        [        1        ]            
From the formula [1], a natural frequency ωn and a damping factor ζ of the conventional ADPLL frequency synthesizer 100 are represented by the following formulas [2] and [3], respectively.
                              ω          n                =                              ρ                    ⁢                      f            R                                              [        2        ]                                ζ        =                              1            2                    ⁢                      α                          ρ                                                          [        3        ]            
As is clear from these formulas, the phase domain transfer function Hcl of the conventional ADPLL frequency synthesizer 100 has no term including the control sensitivity KDCO of the digital controlled oscillator 101 due to an effect produced by the DCO Gain normalization circuit 111. Therefore, even if the oscillatory frequency of the digital controlled oscillator 101 changes, the phase noise characteristic would not be changed accordingly if the control sensitivity estimation section 102 properly estimates a value of the control sensitivity KDCO at all times so as to cancel out a change amount of an undesired control sensitivity which has been changed in accordance with the changed oscillatory frequency.
However, in the conventional ADPLL frequency synthesizer 100 disclosed in patent document 1 mentioned above, the DCO Gain normalization circuit 111 for correcting the control sensitivity KDCO of the digital controlled oscillator 101 is provided in a loop path. Thus, a delay caused by the DCO Gain normalization circuit 111 is generated and therefore there is a problem that a PLL operation will become easily unstable. Furthermore, there is also a problem that an electric power consumption increases since the control sensitivity estimation section 102 operates at all times.